In this talk, we will be looking at quantum circuits comprising parametric gates and analyze their expressivity in terms of the space of states that can be generated by a given circuit.
A standard tool in quantum computing are Variational Quantum Simulations (VQS) which form a class of hybrid quantum-classical algorithms for solving optimization problems. For example, the objective may be to find the ground state of a Hamiltonian by minimizing the energy. As such, VQS use parametric quantum circuit designs to generate a family of quantum states (e.g., states obeying physical symmetries) and efficiently evaluate a cost function for the given set of variational parameters (e.g., energy of the current quantum state) on a quantum device. The optimization is then performed using a classical feedback loop based on the measurement outcomes of the quantum device. In the case of energy minimization, the optimal parameter set therefore encodes the ground state corresponding to the given Hamiltonian provided that the parametric quantum circuit is able to encode the ground state. Hence, the design of parametric quantum circuits is subject to two competing drivers. On one hand, the set of states, that can be generated by the parametric quantum circuit, has to be large enough to contain the ground state. On the other hand, the circuit should contain as few parametric quantum gates as possible to minimize noise from the quantum device. In other words, when designing a parametric quantum circuit we want to ensure that there are no redundant parameters.
Thus, I will introduce the dimensional expressivity analysis as a means of analyzing a given parametric design in order to remove redundant parameters as well as any unwanted symmetries. Furthermore, I will discuss the hardware implementation of the dimensional expressivity analysis.